Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

This study used a TSMC 0.18 µm 50 V process to build high-voltage n-LDMOS structure. In the reference device, number of floating poly (poly-2) turns was 7, and width spacing each turn 1 µm. The experiment realized in three steps, i.e., fixing laps by occupying structure, adjusting turn, distance between turns. first step fixed occupy structure chart adjust increased from 7 9 then decreased 5 3 reduction resulted greater maximum electric field an increase breakdown voltage. A comparison 3-turn set with showed 42% field, 4.17 × 103 2.46 (V/cm), voltage (VBK) 30.2 35.84 V. second 1.4, 1.2, 0.8, 0.6 reduced resulting VBK. When 1.4 µm, 1.95 V/cm VBK 85.6 V, 183%. third per-turn group 33% 1.32 345% 134.4